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ELEG 2134 & ELEG 2130: Digital Logic Design

Course Information


Laboratory


Homework Assignments

Number

Due

Assignment

1

Wed, 8/27/08

2.1(e,f,g,i,j), 2.2(e), 2.3(e), 2.5(d,e,j)

2

Wed, 9/3/08

2.6(b,g,h), 2.7(a-d), 2.8(a-d), 2.12 (a-d) {using 2's comp}

3

Wed, 9/17/08

4.6(a,b), 4.7(b,g)

4

Wed, 9/24/08

4.8(a,d,g,h), 4.9(a,c,d,e)

5

Wed, 10/1/08

4.14(a-f), 4.18(a-e)

6

Wed, 10/15/08

Repeat 4.14 & 4.18 for POS, 4.58(a,c,e)

7

Wed, 10/22/08

4.19(b,d,f), 4.59(b,c,f), Repeat 4.59 for POS

8

Wed, 10/29/08

5.3, 5.10, VHDL module (SOP) for BCD to Braille (4 input 4 output)

9

Wed, 11/5/08

6.79, 7.4, 7.5

10

Wed, 11/12/08

7.12, 7.14, 7.16, 7.18, 7.19

11

Wed, 12/3/08

7.46, 7.47, FSM Design Example


Quizzes

Number

Date

Answers

1

Fri, 08/29/08

Quiz 01 (pdf)

2

Fri, 09/05/08

Quiz 02 (pdf)

3

Fri, 09/19/08

Quiz 03 (pdf)

4

Fri, 09/26/08

Quiz 04 (pdf)

5

Fri, 10/03/08

Quiz 05 (pdf)

6

Fri, 10/17/08

7

Fri, 10/24/08

8

Fri, 10/31/08

9

Fri, 11/07/08

10

Fri, 11/14/07

11

Fri, 12/05/07


Exams

Test/Exam

Date

Answers

Test 1:Fri, 09/12/08Test 01 (pdf)
Mid-Term:Fri, 10/10/08
Test 2:Fri, 11/21/08
Final:8:00am, Wed, 12/10/08

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Last modified: Fri Oct 3 16:11:55 CDT 2008

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